# DeepSeek-V4 on SM86: Runbook

This branch contains the SM86 path used to serve a W4A16 DeepSeek-V4 checkpoint
with CUDA graphs. The validated rig is 8x RTX 3090, which is the SM86 Ampere
setup used for the numbers below.

The reproducible result is not one giant request. The winning shape is CUDA
graph decode plus multiple concurrent sequences, which amortizes the TP8
collective cost.

## Hardware and Software

Validated rig:

- 8x NVIDIA RTX 3090, SM 8.6, 24 GiB per GPU.
- Tensor parallel size: 8.
- Python 3.12.12.
- PyTorch 2.11.0+cu130.
- CUDA toolkit 13.0.1 for the native SM86 vLLM rebuild.
- NVIDIA driver 580.126.09.
- NCCL 2.28.9.
- FlashInfer Python wheel `0.6.14+sm89.1`.
- FlashInfer cubin package `0.6.13`.
- vLLM source branch: `sm86-bf16-backend`.
- Base vLLM wheel lineage: `0.23.1rc1.dev904+g8e321cc4f+cu130`.
- Final runtime: rebuilt from this branch with `TORCH_CUDA_ARCH_LIST=8.6`.
- Serving wrappers benchmarked at commit `1e70ccc`; later commits are docs and
  controller recipe updates unless the launch manifest says otherwise.
- Benchmark model path on the rig: `/models/Ablit-W4A16-direct`.
- Intended public model family:
  [`Intel/DeepSeek-V4-Flash-W4A16-AutoRound`](https://huggingface.co/Intel/DeepSeek-V4-Flash-W4A16-AutoRound).
- KV cache dtype: `fp8_ds_mla`.
- Attention backend: `FLASHINFER_MLA_SPARSE_DSV4`.
- MoE backend: `marlin`.

## Model Provenance

The benchmark used the local checkpoint at `/models/Ablit-W4A16-direct`.
That checkpoint was already quantized before this SM86 serving work. We did not
run AutoRound or create the W4A16 weights in this branch.

The intended public upstream model to link for reproduction is
[`Intel/DeepSeek-V4-Flash-W4A16-AutoRound`](https://huggingface.co/Intel/DeepSeek-V4-Flash-W4A16-AutoRound).
Its public config identifies the format as AutoRound W4A16: `quant_method` is
`auto-round`, `bits` is `4`, `group_size` is `128`, and `packing_format` is
`auto_round:auto_gptq`. The same config reports `autoround_version` `0.14.0`.

If a different Hugging Face repository is published for the exact local
`Ablit-W4A16-direct` mirror, replace the model link above with that repository
and keep this distinction: quantization is an input checkpoint property, not an
SM86 backend step.

Critical launch defaults are centralized in:

```bash
scripts/serve_sm86_cudagraph_common.sh
```

Do not hand-copy flags into local scripts. The wrappers print the complete argv,
git revision, import origin, graph settings, and memory knobs at startup.

## Reproduced Results

All rows below were coherent and used the checked-in wrappers verbatim.

| Envelope | Script | Aggregate decode | Per-sequence decode |
| --- | --- | ---: | --- |
| 1 x 262K | `scripts/serve_sm86_262k_cudagraph.sh` | 59.6 tok/s | 59.6 |
| 2 x 176K | `scripts/serve_sm86_176k_2seq_cudagraph.sh` | 81.3 tok/s | 39.3 / 42.0 |
| 3 x 114K | `scripts/serve_sm86_114k_3seq_cudagraph.sh` | 104.5 tok/s | 32.7 / 36.0 / 35.8 |
| 4 x 80K | `scripts/serve_sm86_80k_4seq_cudagraph.sh` | 120.1 tok/s | 29.2 / 30.3 / 30.3 / 30.2 |

Current recommendations:

- Long-context frontier: `1 x 262K`, coherent at about `59.6 tok/s`.
- Throughput champion: `4 x 80K`, coherent at about `120.1 tok/s` aggregate.
- Speculative decode is parked; MTP drafting reduced graph throughput in prior
  testing.

## Publish Summary

For GitHub or Hugging Face release notes:

> This branch serves a pre-quantized DeepSeek-V4 W4A16 checkpoint on SM86
> Ampere GPUs using the BF16/FP8 path, hybrid compressed KV, FlashInfer sparse
> MLA, Marlin MoE, and CUDA graph decode. The validated 8x RTX 3090 frontier is
> 262K context at about 59.6 tok/s. The validated throughput champion is 4
> concurrent 80K sequences at about 120.1 tok/s aggregate. All published numbers
> used the checked-in launch wrappers verbatim.

Minimum reproduction command:

```bash
scripts/serve_sm86_262k_cudagraph.sh
```

Maximum-throughput reproduction command:

```bash
scripts/serve_sm86_80k_4seq_cudagraph.sh
```

## Commands

Start the best long-context server:

```bash
scripts/serve_sm86_262k_cudagraph.sh
```

Start the throughput champion:

```bash
scripts/serve_sm86_80k_4seq_cudagraph.sh
```

Other validated sequence rungs:

```bash
scripts/serve_sm86_176k_2seq_cudagraph.sh
scripts/serve_sm86_114k_3seq_cudagraph.sh
```

The served model names are set by the wrappers:

- `ablit-w4a16-sm86-262k-cudagraph`
- `ablit-w4a16-sm86-176k-2seq-cudagraph`
- `ablit-w4a16-sm86-114k-3seq-cudagraph`
- `ablit-w4a16-sm86-80k-4seq-cudagraph`

## Why These Envelopes

On this hardware, the KV pool and CUDA graph workspace share a very small
remaining memory window after weights and fixed runtime allocations.

Important knobs:

- `VLLM_MEMORY_PROFILER_ESTIMATE_CUDAGRAPHS=0` gives back vLLM's conservative
  graph reservation estimate. Without this, usable KV pool size is much lower.
- `--block-size 256` is required for these KV block counts.
- `--num-gpu-blocks-override` is hard-pinned per wrapper.
- `--max-num-batched-tokens 512` is used on multi-sequence envelopes to reduce
  workspace pressure.
- CUDA graph capture sizes are set to match the sequence target, for example
  `1,4` with `max_cudagraph_capture_size=4` for the 4-sequence server.

Do not infer capacity from `gpu_memory_utilization` alone. The wrappers pin the
actual KV block count because the automatic profiler and graph workspace can
otherwise drift by enough to fail at startup.

## Verification Checklist

Before benchmarking, confirm these lines in the server log:

- `git_rev` is the expected branch revision.
- `vllm.envs_origin` points at this checkout, not an unrelated site package.
- `kv_cache_dtype=fp8_ds_mla`.
- `attention_backend=FLASHINFER_MLA_SPARSE_DSV4`.
- `VLLM_MEMORY_PROFILER_ESTIMATE_CUDAGRAPHS=0`.
- `num_gpu_blocks_override` matches the selected wrapper.
- Graph capture reaches 100% for the requested capture sizes.

If graph capture does not happen, rerun with:

```bash
CUDAGRAPH_DISPATCH_DEBUG=1 scripts/serve_sm86_262k_cudagraph.sh
```

## Known Non-Goals

- `393K+` single-sequence context is not a published envelope for 24 GiB 3090s.
  It missed the graph/pool memory window by about 30 MiB in this stack.
- Full `2 x 262K` concurrency is not expected to seat without a new workspace
  reduction. It needs at least 2048 KV blocks plus size-2 graph workspace.
- CUDA P2P was unavailable on the tested rig, so TP8 NCCL allreduce remains the
  dominant graph-interior cost.

## Debug Notes

The rank0 graph trace showed the decode step dominated by TP8 allreduce:

- NCCL allreduce: about 17.5 ms per graph step.
- FlashInfer sparse MLA decode: about 1.9 ms per graph step.
- Marlin linear kernels: about 2.2 ms per graph step.
- Marlin MoE WNA16 kernels: about 1.0 ms per graph step.

Concurrency improves aggregate throughput because the per-trip collective cost
is amortized across active sequences.

## Source Links

- DeepSeek-V4 technical report: https://arxiv.org/html/2606.19348v1
- CSA/HCA explanation: https://prathamp.com/blog/deepseek-v4-csa-and-hca/
- Ampere community fork: https://github.com/Lasimeri/vllm-dsv4-ampere
- Rank0 graph trace: 227-launch torch trace, summary numbers in Debug Notes (raw trace available on request).
  `rank0.trace.json.gz`