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Datasets:
AbiralArch
/
hardware-verilogeval-v2
like
0
Tasks:
Text Generation
Modalities:
Text
Formats:
json
Languages:
code
Size:
< 1K
Tags:
hardware
rtl
verilog
systemverilog
fpga
asic
+ 2
Libraries:
Datasets
pandas
Croissant
+ 1
Dataset card
Data Studio
Files
Files and versions
xet
Community
1
refs/convert/parquet
hardware-verilogeval-v2
/
default
111 kB
1 contributor
History:
1 commit
parquet-converter
Update parquet files
01de39d
verified
4 months ago
test
Update parquet files
4 months ago